1 PI6C4911505 rev. b 12/19/12 pi6c20800b features ? ? 5 lvpecl outputs ? ? up to 1.5ghz output frequency ? ? ultra low additive phase jitter: < 0.03 ps (typ) (diferential 156.25mhz, 12khz to 20mhz integration range) ? ? two selectable inputs ? ? low delay from input to output (tpd typ. 1.5ns) ? ? 3.3v power supply ? ? industrial temperature support ? ? tssop-20 package p i 6 c 49115 0 5 block diagram pin confguration (20-pin tssop) description fe PI6C4911505 is a high performance fanout bufer device - which supports up to 1.5ghz frequency. fe device has 2 select - able clock inputs that can accept most diferential clock sources. fis device is ideal for systems that need to distribute low jitter clock signals to multiple destinations. applications ? ? networking systems including switches and routers ? ? high frequency backplane based computing and telecom platforms high performance 1:5 lvpecl fanout buffer 1 2 3 nq1 4 q2 5 q1 6 q3 7 clk0 8 nq2 v dd v dd nclk1 v ee nclk0 nq3 20 19 18 17 16 15 14 13 q0 nq0 clk1 clk_en clk_sel 9q4 12 v dd 10nq4 11 12-0313
2 PI6C4911505 rev. b 12/19/12 2 PI6C4911505 rev. a 12/19/12 pin # pin name ty pe description 1, 2 q0 nq0 output lvpecl output clock 3, 4 q1 nq1 output lvpecl output clock 5, 6 q2 nq2 output lvpecl output clock 7, 8 q3 nq3 output lvpecl output clock 9, 10 q4 nq4 output lvpecl output clock 11, 18, 20 v dd power power supply 12 clk_sel input pulldown clock input source selection pin 13, 14 clk0 nclk0 input pulldown pullup diferential clock input 15 v ee power negative power supply 16, 17 clk1 nclk1 input pulldown pullup diferential clock input 19 clk_en input pullup clock output enable/ disable pinout table PI6C4911505 high performance 1:5 lvpecl fanout bufer 12-0313
3 PI6C4911505 rev. b 12/19/12 3 PI6C4911505 rev. a 12/19/12 function table table 1: input select function clk_sel function 0 clk0, nclk0 1 clk1, nclk1 table 2: output mode select function clk_en outputs q0:q4 nq0:nq4 0 disabled; low disabled; high 1 enabled enabled PI6C4911505 high performance 1:5 lvpecl fanout bufer 12-0313
4 PI6C4911505 rev. b 12/19/12 4 PI6C4911505 rev. a 12/19/12 dc electrical specifcations - differential inputs symbol parameter min. ty p. max. units i ih input high current: clk0, clk1 input = v dd 200 ua input high current: nclk0, nclk1 input = v dd 10 ua i il input low current: clk0, clk1 input = gnd -200 ua input low current: nclk0, nclk1 input = gnd -200 ua c in input capacitance 4 pf v id input diferential amplitude pk-pk 0.15 v dd -0.85 v v cm common model input voltage gnd + 0.5 v dd -0.85 v power supply characteristics and operating conditions symbol parameter test condition min. ty p. max. units v dd core supply voltage 3.135 3.3 3.465 v i dd power supply current all outputs unloaded 160 ma t a ambient operating temperature -40 85 c maximum ratings (above which the useful life may be impaired. for user guidelines, not tested) storage temperature ................................................... - 55 to +150oc s upply voltage to ground potential (v dd ) ............. - 0.5 to +4.6v inputs (referenced to gnd) ............................. -0.5 to v dd +0.5v c lock output (referenced to gnd)................. -0.5 to v dd +0.5v s oldering temperature (max of 10 seconds) .................... +260oc latch up .................................................................................. 200ma note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. fis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. PI6C4911505 high performance 1:5 lvpecl fanout bufer 12-0313
5 PI6C4911505 rev. b 12/19/12 5 PI6C4911505 rev. a 12/19/12 dc electrical specifcations- lvpecl outputs parameter description conditions min. ty p. max. units v oh output high voltage v dd =3.3v 2.1 2.6 v v ol output low voltage v dd =3.3v 1.3 1.8 v dc electrical specifcations - lvcmos inputs symbol parameter conditions min. ty p. max. units i ih input high current input = v dd 200 ua i il input low current input = gnd -200 ua v ih input high voltage v dd =3.3v 2.0 v dd +0.3 v v il input low voltage v dd =3.3v -0.3 0.8 v PI6C4911505 high performance 1:5 lvpecl fanout bufer 12-0313
6 PI6C4911505 rev. b 12/19/12 6 PI6C4911505 rev. a 12/19/12 ac electrical specifcations parameter description conditions min. ty p. max. units f out clock output frequency lvpecl 1500 mhz t r output rise time from 20% to 80% 150 ps t f output fall time from 80% to 20% 150 ps t odc output duty cycle frequency<650mhz 48 52 % v pp output swing single-ended lvpecl outputs 400 mv t j bufer additive jitter rms 0.03 ps t sk output skew 5 outputs devices, outputs in same bank, with same load, at dut. 40 ps t pd propagation delay 1500 ps PI6C4911505 high performance 1:5 lvpecl fanout bufer 12-0313
7 PI6C4911505 rev. b 12/19/12 7 PI6C4911505 rev. a 12/19/12 confguration test load board termination for lvpecl v 100 150 z = 50 l = 0 ~ 10in 150 device o z = 50 o dd tla tla application information wiring the differential input to accept single ended levels figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is gener - ated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio of r1 and r2 might need to be adjusted to postion the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r1/r2 = 0.609. figure 1. single-ended input to dif ferential input device single ended clock input v dd r1 1k r2 1k c1 0.1 clk nclk PI6C4911505 high performance 1:5 lvpecl fanout bufer 12-0313
8 PI6C4911505 rev. b 12/19/12 8 PI6C4911505 rev. a 12/19/12 ordering information (1-3) ordering code package code package description PI6C4911505lie l 20-pin, tssop, pb-free and green notes: 1. 1fermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. e = pb-free and green 3. adding an x sufx = tape/reel date: 05/03/12 description: 20-pin, 173mil wide tssop package code: l document control #: pd-1311 revision: f notes: 1. refer jedec mo-153f/ac 2. controlling dimensions in millimeters 3. package outline exclusive of mold flash and metal burr 12-0373 packaging mechanical: 20-pin tssop (l) PI6C4911505 high performance 1:5 lvpecl fanout bufer 12-0313
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